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Vectored Interrupt Controller
18.2.2.9 Vector Address Register (VECTADDR)
The Vector Address Register contains the ISR address of the currently active interrupt.
Reading this register provides the address of the ISR, and indicates to the priority hard-
ware that the interrupt is being serviced. Writing to this register indicates to the priority
hardware that the interrupt has been serviced.
The ISR can read the VECTADDR Register:
• When an IRQ interrupt is generated at the end of the ISR.
• When the VECTADDR Register is written to.
• To update the priority hardware.
Reading or writing to the register at other times can cause incorrect operation.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:0 VectorAddr
18.2.2.10 Default Vector Address Register (DEFVECTADDR)
This register contains the default ISR address. This address is used for non-vectored IRQs.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:0
18-12
Table 18-19. VECTADDR Register
31
30
29
28
27
0
0
0
0
0
RW
RW
RW
RW
RW
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
Table 18-20. VECTADDR Fields
NAME
ISR Address Reading returns the address of the currently active ISR.
Writing clears the interrupt.
Table 18-21. DEFVECTADDR Register
31
30
29
28
27
0
0
0
0
RW
RW
RW
RW
RW
15
14
13
12
11
0
0
0
0
RW
RW
RW
RW
RW
Table 18-22. DEFVECTADDR Fields
NAME
Default ISR Handler Address Contains the address of the default
Default VectorAddr
ISR handler.
26
25
24
23
VectorAddr
0
0
0
0
RW
RW
RW
RW
10
9
8
7
VectorAddr
0
0
0
0
RW
RW
RW
RW
0x030
0xFFFFF000 +
DESCRIPTION
26
25
24
23
Default VectorAddr
0
0
0
0
0
RW
RW
RW
RW
10
9
8
7
Default VectorAddr
0
0
0
0
0
RW
RW
RW
RW
0x034
0xFFFFF000 +
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22
21
20
19
18
0
0
0
0
0
RW
RW
RW
RW
RW
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
22
21
20
19
18
0
0
0
0
0
RW
RW
RW
RW
RW
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RW
RW
1
0
0
0
RW
RW
17
16
0
0
RW
RW
1
0
0
0
RW
RW
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