Table 4-28. Status Register; Table 4-29. Status Fields; Raw Interrupt Status Register (Status) - Sharp LH79524 User Manual

Color Liquid Crystal Display Controller

4.5.3.8 Raw Interrupt Status Register (STATUS)

STATUS is the Raw Interrupt Status Register. The status of the interrupts without masking
applied is contained in this register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT NAME
31:5
4
3
2
1
0
4-32

Table 4-28. STATUS Register

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
0 0 0 0
RO RO RO RO RO
/// Reserved Reading returns 0. Write the reset value.
AMBA AHB Master Bus Error Status Indicates that the CLCDC AHB master
has encountered a bus error response from a slave.
MBEI
1 = Interrupt asserted
0 = No interrupt
Vertical Compare Set to 1 when one of the four vertical regions selected in the
CONTROL register is reached.
VCI
1 = Interrupt asserted
0 = No interrupt
LCD Next Base Address Update Mode dependent; set to 1 when the Current
Base Address registers have been successfully updated with the data from Next
Address registers. Signifies that a new Next Address can be loaded if double buff-
BUI
ering is in use.
1 = Interrupt asserted
0 = No interrupt
FIFO Underflow Set to 1 when either the upper or lower DMA FIFOs have been
accessed when empty, resulting in an underflow condition
FUI
1 = Interrupt asserted
0 = No interrupt
/// Reserved Reading returns 0. Write the reset value.
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFF4000 + 0x20

Table 4-29. STATUS Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
VCI BUI
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
FUI ///
0 0
RO RO