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UARTs
BIT
4
3
2
1
0
9BIT
0
0
0
0
0
1
16-16
Table 16-20. UARTLCR_H Fields (Cont'd)
NAME
FIFO Enable Buffers This bit not only enables and disables the FIFO buffers,
but also controls the mode. When the FIFO is enabled, it is used to buffer receive
and transmit data. When the FIFO is disabled, the UART is in Character Mode,
using just one line in the FIFO to store a single character.
FEN
1 = Enables transmit and receive FIFO buffers (FIFO Mode).
0 = FIFOs are disabled (Character Mode); that is, the FIFOs become
one-byte-deep holding registers.
Frame Stop Bits This bit sets the number of Stop bits.
1 = Two Stop bits are transmitted at the end of the frame. The receive logic does
STP2
not check for two Stop bits being received.
0 = One Stop bit
Even Parity Select Bits [7], [2], and [1] work together to set up the parity. See
EPS
Table 16-21.
Parity Enable Bits [7], [2], and [1] work together to set up the parity. See
PEN
Table 16-21.
SEND BREAK This bit commands the UART to enter a Break condition. This
bit must be asserted for at least one complete frame transmission time in order
to generate a break condition. The transmit FIFO contents remain unaffected
during a break condition. For normal use, this bit must be cleared to 0.
BRK
1 = A LOW level is continually output on the UARTTXD output, after completing
transmission of the current character
0 = No Break
Table 16-21. Truth Table for 9BIT, SPS, EPS, and PEN bits
SPS
EPS
PEN
X
X
0
Not transmitted or checked
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
1
1
1
1
0
For transmission, ADDRESS TRANSMIT is transmitted as
X
X
X
the parity bit for the frame. If the received parity bit = 1, then the
PARITY-ERROR/ADDRESS RECEIVED error is generated.
DESCRIPTION
RESULTANT PARITY BIT (TRANSMITTED OR CHECKED)
Version 1.0
LH79524/LH79525 User's Guide
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