Figure 2-3. Simplified N-Bit Sar Architecture; Clock Generator - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

2.1.3 Clock Generator

The ADC has a programmable measurement clock derived from the ADC peripheral clock
generated by the RCPC. The clock source is selectable from HCLK or the System oscilla-
tor clock, and can be prescaled. The clock supplies the time base for the measurement
sequencer and the successive-approximation circuitry. Higher clock frequencies allow
faster measurement throughput. Slower clock frequencies allow more settling time for a
measurement and can reduce ADC power consumption. If the clock is too slow, the sam-
ple-and-hold amplifier on the ADC input may droop before the measurement is complete.
2.1.4 Brownout Detector
The Brownout Detector is an asynchronous comparator that compares a divided version
of the 3.3 V supply and a bandgap-derived reference voltage. If the supply dips below a
trip point, the Brownout Detector sets a bit in the IS Register (see Section 2.2.2.8). An
interrupt is directly connected to the VIC. This allows the SoC to notify peripherals of an
impending shutdown and provides the ADC with time to save its state.
The Brownout detector also indicates brownout if the clock is off (PWM bits of PC register
are 0b00 or 0b11). In addition, the Brownout Detector indicates a brownout condition on
startup until the VDDA pin rises above the trip point.
2.1.5 SAR Architecture
While there are various SAR implementations, the basic architecture is simple. Figure 2-3
shows this architecture.
ANALOG IN TRACK/HOLD
VREF

Figure 2-3. Simplified N-bit SAR Architecture

Version 1.0
Analog-to-Digital Converter/Brownout Detector
VIN
COMPARATOR
+
VDAC
_
N-BIT
DAC
N
N-BIT
REGISTER
SAR
LOGIC
DIGITAL DATA OUT
(SERIAL or PARALLEL)
LH79525-54
2-5