Table 7-64. Sturnx Register; Table 7-65. Sturnx Fields; Static Memory Turn Around Delay Registers (Sturnx) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

7.5.2.27 Static Memory Turn Around Delay Registers (STURNx)

The Static Memory Turn Around Delay Registers enable programming the number of bus
turnaround cycles.
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
To prevent bus contention on the external memory data bus, the BTC field controls the
number of bus turnaround cycles added between static memory read and write accesses.
The BTC field also controls the number of turnaround cycles between static memory and
dynamic memory accesses.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS NAME
31:4
3:0

Table 7-64. STURNx Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 7-65. STURNx Fields

/// Reserved Reading returns 0. Write the reset value.
Bus Turnaround Cycles SRAM Wait State time for Write accesses after the
first Read:
BTC
Bus Turnaround Cycles = (BTC + 1) HCLK cycles
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x218 for STURN0
0xFFFF1000 + 0x238 for STURN1
0xFFFF1000 + 0x258 for STURN2
0xFFFF1000 + 0x278 for STURN3
FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 1
RO RO RO RW RW
17 16
0 0
RO RO
1 0
BTC
1 1
RW RW
7-59