Table 12-12. Ris Register; Table 12-13. Ris Fields; Table 12-14. Mis Register; Table 12-15. Mis Fields - Sharp LH79524 User Manual

Real Time Clock

12.2.2.6 Raw Interrupt Status Register (RIS)

Reading this register gives the current raw status value of the RTC interrupt prior to mask-
ing. Writing has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:1
0
12.2.2.7 Masked Interrupt Status Register (MIS)
Reading the MIS register gives the current masked status value of the RTC interrupt. Writ-
ing has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:1
0
12-6
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0
RO RO RO RO RO
/// Reserved Reading returns 0. Values written cannot be read.
Raw Interrupt Status Contains the raw state (prior to masking) of the RTC Interrupt.
RIS
1 = RTC Interrupt asserted
0 = RTC Interrupt not asserted
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0
RO RO RO RO RO
/// Reserved Reading returns 0. Values written cannot be read.
Masked Interrupt Status Contains the masked interrupt state of the RTC Interrupt.
MIS
1 = RTC Interrupt unmasked and asserted
0 = RTC Interrupt masked or not asserted

Table 12-12. RIS Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFE0000 + 0x14

Table 12-13. RIS Fields

DESCRIPTION

Table 12-14. MIS Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFE0000 + 0x18

Table 12-15. MIS Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
RIS
0 0
RO RO
17 16
0 0
RO RO
1 0
MIS
0 0
RO RO