Table 12-8. Cr Register; Table 12-9. Cr Fields; Table 12-10. Imsc Register; Table 12-11. Imsc Fields - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

12.2.2.4 Control Register (CR)

CR allows software to enable the RTC and determine its operational status.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT NAME
31:1
0 START
12.2.2.5 Interrupt Mask Set or Clear Register (IMSC)
IMSC controls the masking of the interrupt generated by the RTC. Reading this register
returns the current mask value of the RTC Interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:1
0
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
/// Reserved Unpredictable values when read. Write the reset value.
RTC Start The RTC can be enabled by writing a 1 to this bit. Once enabled, any writes to
this bit have no effect on the RTC until a system reset. Reading returns the status of the RTC.
1 = RTC enabled
0 = RTC disabled (read only)

Table 12-10. IMSC Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Values written cannot be read.
Interrupt Mask Set or Clear
IMSC
1 = Interrupts unmasked, asserted to VIC when generated
0 = Interrupts masked and not asserted to the VIC

Table 12-8. CR Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE0000 + 0x0C

Table 12-9. CR Fields

DESCRIPTION
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE0000 + 0x10

Table 12-11. IMSC Fields

DESCRIPTION
Version 1.0
Real Time Clock
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RW
17 16
0 0
RO RO
1 0
0 0
RO RW
12-5