Figure 2-4. Example Of A 4-Bit Sar Adc Operation - Sharp LH79524 User Manual

Analog-to-Digital Converter/Brownout Detector
The analog input voltage (VIN) is held on a track/hold. The N-bit register is set to midscale
(100...0, where the most-significant bit is set to 1) to implement the binary search algo-
rithm. This forces the DAC output (VDAC) to be VREF ÷ 2, where VREF is the reference
voltage provided to the ADC. Then a comparison is performed to determine whether VIN
is less than, or greater than VDAC:
• If VIN is less than VDAC, the comparator output is a logic LOW and the most-significant
bit of the N-bit register is cleared to 0.
• If VIN is greater than VDAC, the comparator output is a logic HIGH (or 1) and the
most-significant bit of the N-bit register remains set to 1.
The SAR control logic then moves to the next bit down, forces that bit HIGH, and conducts
another comparison. The SAR control logic repeats this sequence until it reaches the
least-significant bit. When the conversion is complete, the N-bit digital word is available in
the register.
Figure 2-4 shows an example of a 4-bit conversion. In this figure, the y-axis and the bold
line show the DAC output voltage. In this example:
1. The first comparison shows that VIN < VDAC. Consequently, bit 3 is 0. The DAC is
then set to ob0100 and the second comparison is conducted.
2. In the second comparison, VIN > VDAC, so bit 2 remains at 1. The DAC is then set to
0b0110 and the third comparison is conducted.
3. In the third comparison, bit [1] is set to 0 and the DAC is then set to 0b0101 for the last
comparison.
4. In the final comparison, bit 0 remains at 1 because VIN > VDAC.
2-6
VDAC
VREF
3/4 VREF
1/2 VREF
1/4 VREF
BIT 3 = 0 BIT 2 = 1
(MSB)

Figure 2-4. Example of a 4-bit SAR ADC Operation

Version 1.0
LH79524/LH79525 User's Guide
BIT 1 = 0 BIT 0 = 1
(LSB)
VIN
TIME
LH79525-55