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LH79524/LH79252 User's Guide
Chapter 17 - Universal Serial Bus Device
17.1 Theory of Operation ..................................................................................... 17-1
17.2 Register Reference ...................................................................................... 17-8
16.3.2.3 Flag Register (UARTFR) .............................................................. 16-11
16.3.2.4 IrDA Low-Power Counter Register (UARTILPR) .......................... 16-12
16.3.2.5 Integer Baud Rate Divisor Register (UARTIBRD) ........................ 16-13
16.3.2.6 Fractional Baud Rate Divisor Register (UARTFBRD) .................. 16-14
16.3.2.7 Line Control Register (UARTLCR_H)........................................... 16-15
16.3.2.8 UART Control Register (UARTCR) .............................................. 16-17
16.3.2.9 Interrupt FIFO Level Select Register (UARTIFLS) ....................... 16-19
16.3.2.10 Interrupt Mask Set/Clear Register (UARTIMSC) ........................ 16-20
16.3.2.11 Raw Interrupt Status Register (UARTRIS) ................................. 16-22
16.3.2.12 Masked Interrupt Status Register (UARTMIS) ........................... 16-24
16.3.2.13 Interrupt Clear Register (UARTICR)........................................... 16-26
16.3.2.14 UART0 DMA Control Register (DMACTRL) ............................... 16-27
17.1.1 Endpoints .............................................................................................. 17-2
17.1.1.1 Isochronous Endpoints ................................................................... 17-3
17.1.2 FIFOs .................................................................................................... 17-3
17.1.3 Serial Interface Engine (SIE) ................................................................. 17-3
17.1.3.1 OUT_PKT_RDY Interrupt Operation for Endpoint 0....................... 17-3
17.1.4 DMA Interface ....................................................................................... 17-4
17.1.4.1 DMA Modes.................................................................................... 17-4
17.1.4.2 DMA Bus Cycles............................................................................. 17-4
17.1.4.3 Bus Errors....................................................................................... 17-4
17.1.5 DMA Operation...................................................................................... 17-5
17.1.5.1 DMA Mode 0: OUT Endpoints ........................................................ 17-5
17.1.5.2 DMA Mode 0: IN Endpoints ............................................................ 17-5
17.1.5.3 DMA Mode 1: OUT Endpoints ........................................................ 17-6
17.1.5.4 DMA Mode 1: IN Endpoints ............................................................ 17-7
17.1.6 Remote Wakeup.................................................................................... 17-7
17.2.1 Memory Map ......................................................................................... 17-8
17.2.2 Register Definitions ............................................................................. 17-10
17.2.2.1 Function Address Register (FAR)................................................. 17-10
17.2.2.2 Power Management Register (PMR)............................................ 17-11
17.2.2.3 Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR) ....................... 17-12
17.2.2.4 Interrupt Register for OUT Endpoint 1 and 2 (OIR) ...................... 17-13
17.2.2.5 Interrupt Register for common USB interrupts (UIR).................... 17-14
17.2.2.6 IN Interrupt Enable Register (IIE) ................................................. 17-15
17.2.2.7 OUT Interrupt Enable Register (OIE) ........................................... 17-16
17.2.2.8 Interrupt Enable Register (UIE) .................................................... 17-17
17.2.2.9 Frame Number Registers (FRAMEx) ........................................... 17-18
17.2.3 Indexed Registers ............................................................................... 17-19
17.2.3.1 Index Register (INDEX) ................................................................ 17-19
17.2.3.2 IN Maximum Packet Size Register (INMAXP).............................. 17-20
17.2.3.3 Control Status Register for EP 0 (CSR0) ..................................... 17-21
17.2.3.4 Control Status Register 1 for IN EP 1, 2, and 3 (INCSR1) ........... 17-23
17.2.3.5 Control Status Register 2 for IN EP 1, 2, and 3 (INCSR2) ........... 17-25
Version 1.0
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