Table 2-20. Fs Register; Table 2-21. Fs Fields; Fifo Status Register (Fs) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

2.2.2.9 FIFO Status Register (FS)

FS is the FIFO Status Register. This Read Only register indicates the FIFO fill status.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:12
11:8
7:4
3
2
1
0
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Write Pointer FIFO Location Contains the index of the memory
WRPTR location in the result FIFO array where the next measurement
result will be stored.
Read Pointer FIFO Location Contains the index to the location
RDPTR in the result FIFO array where the next measurement result will be
read. Reads from the RR register increment this value.
FIFO Full
FFF
1 = FIFO is full
0 = FIFO is not full
FIFO Empty
FEMPTY
1 = FIFO is empty
0 = FIFO is not empty
FIFO Overrun Status Bit This bit is 1 when the receive logic tries
to place data into the FIFO after it has been completely filled. When
new data is received, the FOVRNDET bit is asserted and the newly
received data is discarded. This process repeats for each time new
data is received, until at least one empty FIFO entry exists. When
FOVRNDET
FOVRNDET is set to 1, an interrupt request is generated.
1 = Logic tried to place data into a full receive FIFO and is
0 = FIFO has not experienced an overrun
FIFO at Watermark
FGTEWATERMRK
1 = FIFO is at or above watermark level
0 = FIFO has fewer entries than the watermark level
Analog-to-Digital Converter/Brownout Detector

Table 2-20. FS Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
WRPTR
0 0 0 0
RO RO RO RO
0xFFFC3000 + 0x20

Table 2-21. FS Fields

DESCRIPTION
requesting an interrupt
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
RDPTR FFF
0 0 0 0 1
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO
2-21