Table 13-30. Pclksel1 Register; Table 13-31. Pclksel1 Fields; Peripheral Clock Select Register 1 (Pclksel1) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.13 Peripheral Clock Select Register 1 (PCLKSEL1)

This register allows selection of the clock source for the USB, ADC, and SSP peripherals.
Note that the default source for the USB clock following reset is HCLK. For virtually all
designs, this must be programmed to the USB PLL following reset. Failing to do this could
result in the USB Client not operating properly.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:4
3
2
1
0

Table 13-30. PCLKSEL1 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-31. PCLKSEL1 Fields

/// Reserved Reading returns 0. Write the reset value.
USB Peripheral Clock Source Following reset, HCLK is the source. In almost
all cases, this should be programmed to 1 following reset.
USB
1 = USB PLL Clock
0 = System Clock (HCLK)
ADC Peripheral Clock Source
ADC
1 = System Clock Oscillator frequency
0 = System Clock (HCLK)
SSP Peripheral Clock Source
SSP
1 = System Clock Oscillator frequency
0 = System Clock (HCLK)
/// Reserved Reading returns 0. Write the reset value.
Reset, Clock, and Power Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE2000 + 0x34
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
USB ADC
0 0 0 0 0
RO RO RO RW RW
17 16
0 0
RO RO
1 0
SSP ///
0 0
RW RW
13-23