Table 26-17. Uart2 Register Summary (Register Bank 0); Table 26-18. Uart2 Register Summary (Register Bank 1) - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary

Table of Contents

26.15 UART2 Registers

Base address: 0xFFFC2000

Table 26-17. UART2 Register Summary (Register Bank 0)

DLAB TYPE RESET

LH75400/01/10/11 (Preliminary) User's Guide

Transmit Buffered Data Register

Receive Buffered Data Register

BRGA Divisor Least Significant Byte Register.

The DLAB bit in the LCR Register must be set

to access this register.

BRGA Divisor Most Significant Byte Register.

The DLAB bit in the LCR Register must be set

to access this register.

General Enable Register

General Interrupt Register/Bank Register

Line Control Register

Loopback Control Register

Line Status Register

Address/Control Character Register 0

Transmit Buffered Data Register

Receive Buffered Data Register

Transmit Character Flag Register

Receive Character Flag Register

General Interrupt Register/Bank Register

(same register as in bank 0)

Timer Control Register

Timer Status Register

Loopback Control Register

FIFO Level Register

Receive Command Register

Receive Machine Status Register

Transmit Command Register

Internal Command Register

General Status Register