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Chapter 20
UART2
The UART2 peripheral offers similar functionality to the industry standard 82510. It per-
forms serial-to-parallel conversion on data received from a peripheral device and parallel-
to-serial conversion on data transmitted to the peripheral device. The CPU reads and
writes data and control/status information through the AMBA APB interface. The transmit
and receive paths are buffered with internal FIFO memories that support a programmable
depth from 1 to 4.
Figure 20-1 shows a block diagram of the UART.
APB
BUS
INTERFACE
INTERRUPT
TO VIC
Figure 20-1. UART2 Block Diagram
Tx FIFO
TRANSMITTER
Rx FIFO
BAUD RATE
GENERATORS/TIMERS
6/17/03
UART2TX
RECEIVER
UART2RX
LH754xx-14
20-1
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