Table of Contents
Advertisement
LH75400/01/10/11 (Preliminary) User's Guide
23.1 ADC Features............................................................................................... 23-3
23.2 ADC Theory of Operation............................................................................. 23-7
23.3 ADC Programmer's Model ........................................................................... 23-8
24.1 LCD Panel Signal Multiplexing Details ......................................................... 24-1
22.3.2.13 Transmit Buffer ........................................................................... 22-23
22.3.2.14 Transmit Buffer Descriptor Field................................................. 22-24
22.3.2.15 CAN Receive Buffer ................................................................... 22-26
22.3.2.16 Receive Buffer Descriptor Field.................................................. 22-27
22.3.2.17 Acceptance Code Registers ....................................................... 22-27
22.3.2.18 Acceptance Mask Registers (AMR0 - AMR3) ............................ 22-27
22.3.2.19 Receive Message Counter Register........................................... 22-28
22.3.2.20 Receive Buffer Start Address Register....................................... 22-29
22.3.3 CAN Reset Mode ................................................................................ 22-30
22.3.4 CAN Acceptance Filtering ................................................................... 22-32
23.1.1 Bias-and-Control Network ..................................................................... 23-3
23.1.2 Clock Generator .................................................................................... 23-3
23.1.3 Brownout Detector................................................................................. 23-4
23.1.4 SAR Architecture ................................................................................... 23-5
23.3.1 ADC Registers Summary ...................................................................... 23-8
23.3.2 ADC Register Definitions....................................................................... 23-9
23.3.2.1 High Word Register ........................................................................ 23-9
23.3.2.2 Control Bank Low Word Register ................................................. 23-11
23.3.2.3 Results Register ........................................................................... 23-12
23.3.2.4 Interrupt Masking/Enabling Register ............................................ 23-13
23.3.2.5 Power Configuration Register....................................................... 23-14
23.3.2.6 General Configuration Register .................................................... 23-16
23.3.2.7 Sequence Start Mode Issues ....................................................... 23-17
23.3.2.8 General Status Register ............................................................... 23-18
23.3.2.9 Interrupt Status Register............................................................... 23-19
23.3.2.10 FIFO Status Register.................................................................. 23-20
23.3.2.11 Control Bank Registers............................................................... 23-21
23.3.2.12 Idle High Word Register ............................................................. 23-22
23.3.2.13 Idle Low Word Register .............................................................. 23-23
23.3.2.14 Masked Interrupt Status Register ............................................... 23-24
23.3.2.15 Interrupt Clear Register .............................................................. 23-25
23.3.3 ADC Timing Formulas ......................................................................... 23-26
23.3.4 ADC Interrupts..................................................................................... 23-26
23.3.4.1 Brownout Interrupt ........................................................................ 23-27
23.3.4.2 Pen Interrupt................................................................................. 23-27
23.3.4.3 End-of-Sequence Interrupt ........................................................... 23-27
23.3.4.4 FIFO Watermark Interrupt ............................................................ 23-27
23.3.4.5 FIFO Overrun Interrupt ................................................................. 23-28
6/17/03
Table of Contents
xi
Advertisement
Table of Contents
