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LH75400/01/10/11 (Preliminary) User's Guide
15.2.2.3 Timer 0 Interrupt Control Register
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
Table 15-8. INT_CTRL Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
R
R
R
R
R
Table 15-9. INT_CTRL Register Definitions
BITS
FIELD NAME
31:8
///
7
CAP4_EN
6
CAP3_EN
5
CAP2_EN
4
CAP1_EN
3
CAP0_EN
2
CMP1_EN
1
CMP0_EN
0
OVF_EN
26
25
24
23
///
0
0
0
0
R
R
R
R
10
9
8
7
0
0
0
0
R
R
R
RW
0xFFFC4000 + 0x08
DESCRIPTION
Reserved Read as zero.
Timer 0 Interrupt Enable During Capture 4 Operation
0 = No interrupt request occurs for capture 4.
1 = Interrupt request occurs for capture 4.
Timer 0 Interrupt Enable During Capture 3 Operation
0 = No interrupt request occurs for capture 3.
1 = Interrupt request occurs for capture 3.
Timer 0 Interrupt Enable During Capture 2 Operation
0 = No interrupt request occurs for capture 2.
1 = Interrupt request occurs for capture 2.
Timer 0 Interrupt Enable During Capture 1 Operation
0 = No interrupt request occurs for capture 1.
1 = Interrupt request occurs for capture 1.
Timer 0 Interrupt Enable During Capture 0 Operation
0 = No interrupt request occurs for capture 0.
1 = Interrupt request occurs for capture 0.
Timer 0 Interrupt Enable Upon Compare 1
0 = No interrupt request occurs for compare 1.
1 = Interrupt request occurs for compare 1.
Timer 0 Interrupt Enable Upon Compare 0
0 = No interrupt request occurs for compare 0.
1 = Interrupt request occurs for compare 0.
Timer 0 Interrupt Overflow Enable
0 = No interrupt request occurs when counter overflows.
1 = Interrupt request occurs when counter overflows.
6/17/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
Timers
17
16
0
0
R
R
1
0
0
0
RW
RW
15-13
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