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Reset, Clock, and Power Controller
9.1 RCPC Features
The RCPC provides the following features:
• Manages five Power Modes for minimizing power consumption: Active, Standby, Sleep,
Stop1, and Stop2
• Generates the system clock (HCLK) from either the PLL clock or the PLL-bypassed
(oscillator) clock, divided by 2, 4, 6, 8, ... 30
• Generates three UART clocks from oscillator clock
• Generates the1 Hz RTC clock
• Generates the SSP and LCD clocks from HCLK, divided by 1, 2, 4, 8, 16, 32, or 64
• Provides a selectable external clock output
• Generates system and RTC resets based on an external reset, Watchdog Timer reset,
or soft reset
• Configures seven HIGH/LOW-level or rising/falling edge-trigger external interrupts and
converts them to HIGH-level trigger interrupt outputs required by the VIC
• Generates remap outputs used by the memory map decoder
• Provides an identification register
• Supports external or watchdog reset status.
9.2 RCPC Theory of Operation
The RCPC allows users to control System Reset, clocks, power management, and exter-
nal interrupt conditioning via an AMBA APB interface. This control includes:
• Enabling and disabling various clocks
• Managing power-down sequencing
• Selecting the sources for various clocks.
The RCPC provides for an orderly start-up until the crystal oscillator stabilizes and the
Phase Lock Loop (PLL) acquires lock. In addition, if users want to change the system clock
frequency during normal operation, the RCPC ensures a seamless transition between the
old and new frequencies. Note, however, that the same protection is not available when
changing the frequency of individual peripheral clocks; as a result, the peripheral must be
disabled before the peripheral is changed to a new frequency.
9-2
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
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