Internal Mode Register; Table 20-55. Imd Register; Table 20-56. Imd Register Definitions - Sharp Blue Treak LH75400 User Manual

UART2

20.3.2.23 Internal Mode Register

Register Bank: 2
IMD is the Internal Mode Register. The IMD Register defines the General Device Operat-
ing Mode.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:4
3
2
1
0
20-34
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 20-56. IMD Register Definitions

/// Reserved Do not modify. Read as zero.
///
Reserved Do not modify. Read as one.
Receive FIFO Depth Configures the depth of the Rx FIFO.
RFD
0 = Four bytes
1 = One byte. The FIFO acts as a 1-byte buffer to emulate the 8250A UART.
LAN Mode Enables the UART to recognize and/or match an address using
the 9-bit MCS-51 asynchronous protocol.
LM 0 = Normal Mode
µ
1 = LAN Mode
See the ACTRL0 Register for a complete description of the µLAN Mode.
Loopback/Echo Mode Select Selects either loopback or echo operation,
depending on the operating mode selected by bit [4] of the MCTRL Register.
In Loopback Mode (LC = 1), this bit selects between local and remote loopback:
0 = Local loopback
LEM
1 = Remote loopback
In Echo Mode (LC = 0), this bit selects between echo or non-echo operation:
0 = No echo
1 = Echo operation
LH75400/01/10/11 (Preliminary) User's Guide

Table 20-55. IMD Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0
R R R R
0xFFFC2000 + 0x10
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
///
FRD
0 0 0 1 1
R R R RW RW
17 16
0 0
R R
1 0
µLM
LEM
0 0
RW RW