Receive Timeout Register; Table 18-17. Rxto Register; Table 18-18. Rxto Register Definitions; Table 18-15. Iir/Icr Register (Write Characteristic) - Sharp Blue Treak LH75400 User Manual

Synchronous Serial Port
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0

18.5.2.7 Receive Timeout Register

RXTO is the Receive Timeout Register. This register specifies the number of system
clock cycles that must elapse before the receive timeout. The active bits used in this reg-
ister are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:16
15:0
18-18

Table 18-15. IIR/ICR Register (Write Characteristic)

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
W W W W W

Table 18-16. IIR/ICR Register Definitions (Write Characteristic)

NAME
/// Reserved Writing to these bits has no effect.
Clear Receive Overrun Interrupt A write to these bits clears the Receive
///
Overrun Interrupt, regardless of the data value written.

Table 18-17. RXTO Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 18-18. RXTO Register Definitions

/// Reserved Writing to these bits has no effect. Reading returns 0.
HCLK Wait Periods If 0x0001 ≤ RXTO ≤ 0xFFFF, then RXTO contains the
number of HCLK periods that must elapse from the time the SSP Receive Inter-
rupt has been cleared after a previous data transfer without another SSP Receive
RXTO Interrupt before the Receive Timeout Interrupt is asserted.
RXTO = 0x0000; disables the Rx Timeout function.
Writing any value to this register clears the current Receive Overrun Interrupt.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0
W W W W W
0xFFFC6000 + 0x014
DESCRIPTION
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
RXTO
0 0 0 0
RW RW RW RW RW
0xFFFC6000 + 0x018
DESCRIPTION
6/17/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
0 0 0 0 0
W W W W
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
0 0 0 0 0
RW RW RW RW
17 16
0 0
R R
1 0
0 0
W W
17 16
0 0
R R
1 0
0 0
RW RW