Timing2 Register; Table 13-41. Timing2 Register; Table 13-42. Timing2 Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

13.4.5.4 Timing2 Register

The Timing2 Register is used for various delay values for output signals. All delays are
specified in number of LCD clock (LCDDCLK) periods. The active bits used in this register
are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:9
8:0

Table 13-41. Timing2 Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
SPLVALUE
0 0 0 0 0
RW RW RW RW RW

Table 13-42. Timing2 Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
SPL Pulse Delay Delays SPL pulse during vertical front and back porches.
The delay must be programmed to a value greater than HSW + HBP (see the
CLCD reference for HSW and HBP fields). Program with (delay required – 1).
SPLVALUE
Range from (HSW + HBP) to 2 × (HSW + HBP) + HFP. Recommended
delay = HSW + HBP.
SPL-to-CLS/PS Delay Controls the delay (number of LCDDCLK periods)
PSDEL2/
from the rising edge of SPL to the falling/rising edge of CLS/PS, respectively.
CLSDEL2
Program with (delay required – 1). Range from 3 to 512 cycles.
Color Liquid Crystal Display Controller
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
0 0 0 0 0
RW RW RW RW RW
0xFFFE4000 + 0x00C
FUNCTION
7/15/03
21 20 19 18 17
0 0 0 0
R R R R R
5 4 3 2
PSDEL2/CLSDEL2
0 0 0 0
RW RW RW RW RW
16
0 0
R
1 0
0 0
RW
13-29