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LH75400/01/10/11 (Preliminary) User's Guide
9.2.3.1 Active Mode
Active Mode is the normal Power Mode. The SoC enters this mode after start-up and upon
exiting any other Power Mode. After an External Reset, Watchdog Timer Reset, or Soft
Reset is released, the System Reset is held active for an extra eight system clock cycles
after the PLL is locked.
9.2.3.2 Standby Mode
Standby Mode stops the clocks to the CPU and Watchdog Timer while the rest of the SoC
remains active. Standby Mode is entered when software writes 0b001 to the PWR DWN
SEL field of the Ctrl Register (see Section 9.3.2.1). When an interrupt is received, the
RCPC exits Standby Mode and ensures an orderly transition to Active Mode. An interrupt
should be held active until the RCPC exits Standby Mode.
NOTE: Be sure there are no transmit or receive operations occurring when the LH75400/01/10/11 SoC
9.2.3.3 Sleep Mode
Sleep Mode stops all system clocks, keeping only the PLL and internal oscillators active.
The SoC enters this mode when software writes 0b010 to the PWR DWN SEL field of the
Ctrl Register (see Section 9.3.2.1). When an interrupt is received, the RCPC exits Sleep
Mode and ensures an orderly transition to Active Mode. An interrupt should be held active
until the RCPC exits Sleep Mode.
NOTE: Be sure there are no transmit or receive operations occurring when the LH75400/01/10/11 SoC
9.2.3.4 Stop1 Mode
Stop1 Mode stops all system clocks and disables the PLL, but keeps the internal oscilla-
tors active. The SoC enters this mode when software writes 0b011 to the PWR DWN SEL
field of the Ctrl Register (see Section 9.3.2.1). When an interrupt is received, the RCPC
exits Stop1 Mode and ensures an orderly transition to Active Mode. An interrupt should be
held active until the RCPC exits Stop1 Mode.
NOTE: Be sure there are no transmit or receive operations occurring when the LH75400/01/10/11 SoC
9.2.3.5 Stop2 Mode
Stop2 Mode stops all system clocks and disables both the PLL and the internal oscillator that
feeds it. However, the 32.768 kHz internal oscillator remains active. The SoC enters this
mode when software writes 0b100 to the PWR DWN SEL field of the Ctrl Register (see
Section 9.3.2.1). When an interrupt is received, the RCPC exits Stop2 Mode and ensures an
orderly transition to Active Mode. An interrupt should be held active until the RCPC exits
Stop2 Mode.
NOTE: Be sure there are no transmit or receive operations occurring when the LH75400/01/10/11 SoC
device enters Standby Mode.
device enters Standby Mode.
device enters Stop1 Mode.
device enters Stop2 Mode.
Reset, Clock, and Power Controller
7/15/03
9-5
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