Table 26-21. Canbus Controller Register Summary - Sharp Blue Treak LH75400 User Manual

Register Map
26.17 CANBUS Controller Registers
Base address: 0xFFFC5000
ADDRESS
REGISTER
OFFSET
0x00
MOD
CMR 0x04
SR 0x08
IR 0x0C
IER 0x10
/// 0x14
BTR0 0x18
BTR1 0x1C
/// 0x20
/// 0x24
/// 0x28
ALC 0x02C
ECC 0x30
EWLR 0x34
RXERR 0x38
TXERR 0x3C
0x40
Transmit
Buffer
0x44 - 0x70
0x40
Receive
Window
0x44 - 0x70
ACR0 0x40
ACR1 0x44
ACR2 0x48
ACR3 0x4C
AMR0 0x50
AMR1 0x54
AMR2 0x58
AMR3 0x5C
RMC 0x74
RBSA 0x78
/// 0x7C
/// 0x80 - 0x17C
/// 0x180 - 0x1B0
/// 0x1B4 - 0x1FC
NOTES:
1. The Mode Register sets the behavior of the CAN Controller. Bits can be set or reset from the CPU,
which sees the Mode Register as part of its Read/Write memory. Reserved bits are read as '0'.
2. Receive data is read from same CAN address where transmit data is written (0x40-0x70). However, transmit data may be
read back from 0x180-1B0.
3. The Mode Register sets the behavior of the CAN Controller. Bits can be set or reset from the
CPU, which sees the Mode Register as part of its Read/Write memory. Reserved bits are read as '0'.
26-14

Table 26-21. CANBUS Controller Register Summary

TYPE
OPERATING RESET
MODE MODE
RW RW
W W
R R
R R
RW RW
R RW
R RW
R R
R R
R RW
R RW
R RW
W RW
W RW
R RW
R RW
R RW
R RW
R RW
R RW
R RW
R RW
R RW
R RW
R R
R RW
R RW
R R
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
Mode Register
Command Register
Status Register
Interrupt Register
Interrupt Enable Register
Reserved (returns 00h when read)
Bus Timing 0 Register
Bus Timing 1 Register
Reserved
Reserved
Reserved (returns 00h when read)
Arbitration Lost Capture Register
Error Code Capture Register
Error Warning Limit Register
Receive Error Counter Register
Transmit Error Counter Register
Transmit Frame Information Register
(read back from 0x180)
Transmit Data Information
(read back from 0x184 - 0x1B0)
Receive Frame Information Register
Receive Data Information
Acceptance Code Register 0
Acceptance Code Register 1
Acceptance Code Register 2
Acceptance Code Register 3
Acceptance Mask Register 0
Acceptance Mask Register 1
Acceptance Mask Register 2
Acceptance Mask Register 3
Receive Message Counter Register
Receive Buffer Start Address Register
Reserved
Receive FIFO
Transmit Buffer
Reserved (returns 00h when read)
6/17/03
RESET
NOTES
VALUE
0x01 1
0x00
0x3C
0x00
0x00
—
0x00
0x00
0x00
0x00
0x60
0x00
0x00
2
2
2
2
0x00 3
0x00 3
0x00 3
0x00 3
0x00 3
0x00 3
0x00 3
0x00 3
0x00
0x00
0x7C