Timer Muxing Register; Table 11-11. Timer_Mux Register Definitions - Sharp Blue Treak LH75400 User Manual

I/O Configuration

11.2.2.4 Timer Muxing Register

TIMER_MUX is the Timer Muxing Register. This register allows the secondary function of
the TIMER interface pins to be configured as GPIO. The active bits used in this register
are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:14 CTCAP2B
13:12 CTCAP2A
11:10 CTCAP1B
9:8
11-8
Table 11-10. TIMER_MUX Register
31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
CTCAP2B CTCAP2A CTCAP1B
0 0 0 0
RW RW RW RW RW

Table 11-11. TIMER_MUX Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Pin PF6 /CTCAP2B/CTCMP2B Source
00 = PF6
01 = CTCAP2B
10 = CTCMP2B
11 = PF6
Pin PF5/CTCAP2A/CTCMP2A Source
00 = PF5
01 = CTCAP2A
10 = CTCMP2A
11 = PF5
Pin PF4/CTCAP1B/CTCMP1B Source
00 = PF4
01 = CTCAP1B
10 = CTCMP1B
11 = PF4
Pin PF3/CTCAP1A/CTCMP1A Source
00 = PF3
CTCAP1A
01 = CTCAP1A
10 = CTCMP1A
11 = PF3
PF2/CTCAP0E Source
7 CTCAP0E
0 = PF2
1 = CTCAP0E
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
CTCAP1A
0 0 0 0 0
RW RW RW RW
0xFFFE5000 + 0x0C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
CTCAP0B CTCAP0A
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
0 0
RW RW