Table of Contents
Advertisement
LH79524/LH79525 User's Guide
9.1.1 Setting I
When the I
using two registers, ICHCNT and ICLCNT for timing parameters. When the I
in Slave mode, SCL is provided by the Master.
The equation for calculating the proper number of HCLKs required for setting the proper
SCL clock HIGH and LOW period is:
HCNT = ROUND_UP (MIN_SCL_HIGH
LCNT = ROUND_UP (MIN_SCL_LOW
'ROUND_UP' means to round all fractions up to the next highest integer. The LOW count
is calculated in the same way.
Permissible values for the parameters in the equations are found inTable 9-1. Example
timing results appear in Table 9-2.
2
I
C DATA
RATE (kbit/s)
100
100
100
400
400
400
400
2
C Clock Timing
2
C Module is in Master mode, the serial clock (SCL) is generated from HCLK,
Table 9-1. I
VALUE
k (constant)
MIN_SCL_HIGH
MIN_SCL_LOW
Table 9-2. Sample I
HCLK (MHz)
6.6
9.9
51.6
10.0
15.3
20.0
51.6
× HCLK frequency) – k)
time
× HCLK frequency) – k)
time
2
C Clock Parameters
400 kbit/s
4
0.6 μs
1.3 μs
2
C HIGH Period Counts
SCL HIGH
REQUIRED MIN (μs)
4
4
4
0.6
0.6
0.6
0.6
Version 1.0
2
I
C Module
2
C Module is
100 kbits/s
3
4.0 μs
4.7 μs
SCL HIGH
HCNT
TIME (μs)
24
4.09
37
4.14
204
4.01
2
0.60
6
0.654
8
0.66
27
0.600
9-3
Advertisement
Table of Contents
