Table 16-26. Uartimsc Register; Table 16-27. Uartimsc Fields; Interrupt Mask Set/Clear Register (Uartimsc) - Sharp LH79524 User Manual

UARTs

16.3.2.10 Interrupt Mask Set/Clear Register (UARTIMSC)

UARTIMSC is the Interrupt Mask Register. On a read, this register returns the current value
of the mask on the relevant interrupt. Writing 0 to the particular bit masks the interrupt. Writ-
ing 1 enables the corresponding interrupt. All the bits are cleared to 0 following a System
Reset, which masks all interrupts by default.
The combined UARTx UARTINT, presented to the VIC, is the bitwise logical AND of this
register and the Raw Interrupt register, UARTRIS.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:11
10
9
8
7
16-20

Table 16-26. UARTIMSC Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 16-27. UARTIMSC Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Overrun Error Interrupt Mask When read, returns the current mask for the
OEIM interrupt. Write values:
OEIM
1 = Enable the OEI interrupt
0 = Mask the OEI interrupt
Break Error Interrupt Mask When read, returns the current mask for the
BEIM interrupt. Write values:
BEIM
1 = Enable the BEI interrupt
0 = Mask the BEI interrupt
Parity Error/Address Received Interrupt Mask When read, returns the cur-
rent mask for the PEARIM interrupt. Write values:
PEARIM
1 = Enable the PEARI interrupt
0 = Mask the PEARI interrupt
Framing Error Interrupt Mask When read, returns the current mask for the
FEIM interrupt. Write values:
FEIM
1 = Enable the FEI interrupt
0 = Mask the FEI interrupt
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RW RW RW RW
UART 0: 0xFFFC0000 + 0x038
UART 1: 0xFFFC1000 + 0x038
UART 2: 0xFFFC2000 + 0x038
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
///
0 0 0 0 0
RW RW RW RO RO
17 16
0 0
RO RO
1 0
///
0 0
RW RO