Interrupts - Sharp LH79524 User Manual

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LH79524/LH79525 User's Guide

10.1.7 Interrupts

2
The I
S Converter can assert seven types of interrupts. Only the single combined interrupt,
I2SINTR, goes to the VIC:
• SSPPE — I
ated by I
• ECPE — I
bounds), generated by I
• TXUE — SSP Transmit FIFO Underrun Error Interrupt request, generated by I
verter, locally maskable
• SSPRXINTR — SSP Receive FIFO Service Interrupt request, generated by SSP
• SSPTXINTR — SSP Transmit FIFO Service Interrupt request, generated by SSP
• SSPRORINTR — SSP Receive Overrun Interrupt request, generated by SSP
• SSPRXTOINTR — SSP Receive FIFO Timeout Interrupt request, generated by SSP
All seven interrupts are combined into a single interrupt: I2SINTR. This interrupt super-
sedes SSPINTR.
The status of the seven individual interrupt sources can be read from the MIS or RIS Reg-
ister. Only the I
The SSP mask bits are present, but only as read-only status bits.
10.1.7.1 SSP Protocol Error Interrupt
SSPPE is the SSP Protocol Error Interrupt. This Interrupt is asserted when the SSP and
2
I
S are enabled and the SSP is configured for the wrong frame length. This is a new inter-
rupt and only applies to I
10.1.7.2 External Codec Protocol Error Interrupt
ECPE is the External Codec Protocol Error Interrupt. This Interrupt is asserted when the
2
I
S is operating in slave mode and a frame is transmitted or received with the wrong frame
length. This is a new interrupt and only applies to I
10.1.7.3 Transmit FIFO Underrun Interrupt
TXUE is the Transmit FIFO Underrun Interrupt. This interrupt is asserted when the FIFO
is empty, but a new transmission is begun, causing an underrun of the FIFO. This is a new
2
I
S Converter interrupt, but it is valid for other SSP modes, regardless of whether the I
Converter is enabled. Since the SSP shuts off the master clock once the Transmit FIFO
runs out of data, this error only applies to slave mode transmission.
In the event of a Transmit FIFO Underrun while the I
transmit frame delay pipe so that remaining valid data bits will be shifted out, followed by
a 0. The frame pulse generated to the SSP block by the I
2
If the I
not altered (SSPFSSIN is not suppressed, and logic '0' is not fed into the slave delay pipe).
2
S SSP Protocol Error Interrupt request (Frame size out of bounds), gener-
2
S Converter, locally maskable
2
S External Codec Protocol Error Interrupt request (Frame size out of
2
S Converter, locally maskable
2
S converter specific interrupts can be masked in the I2S IMSC register.
2
S transactions.
S Converter is disabled during an underrun condition, the behavior of the SSP is
2
S transactions.
2
Version 1.0
I
S is enabled, a 0 will be fed into the
2
S Converter is suppressed.
2
S Converter
2
S Con-
2
S
10-11

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