Table 7-45. Wait Register; Table 7-46. Wait Fields; Static Memory Extended Wait Register (Wait) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

7.5.2.18 Static Memory Extended Wait Register (WAIT)

The Static Memory Extended Wait Register is used to time long static memory read and
write transfers (longer than can be supported by the SWAITRD or SWAITWR registers)
when the EW bit of the SCONFIG register is enabled. There is only a single WAIT register.
These registers should only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable. However, if necessary, these control bits
can be altered during normal operation.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS NAME
31:10
9:0

Table 7-45. WAIT Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO
/// Reserved Reading returns 0. Write the reset value.
WAIT External Wait Time Out Wait Time Out = (WAIT+1) x 16 HCLK clock periods
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RW RW RW
0xFFFF1000 + 0x080

Table 7-46. WAIT Fields

FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
WAIT
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW
7-47