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LH79524/LH79525 User's Guide
1.1 Bus Architecture
The LH79524 and LH79525 both internally employ the ARM Advanced Microprocessor
Bus Architecture (AMBA) 2.0 bus and bus protocol. They have four Bus Masters on the
Advanced High-performance Bus (AHB) that control access to the external memory and
the on-chip peripherals. The AHB Bus Masters are:
• The ARM720T core processor
• Direct Memory Access Controller (DMAC) for transfers between memory and an exter-
nal peripheral, or memory.
• Ethernet MAC Controller (EMAC)
• Color LCD Controller (CLDCC).
Except in test mode, the ARM720T processor is the default bus master.
An Advanced Peripheral Bus (APB) bridge is provided to access the various APB periph-
erals. Generally, APB peripherals are serviced by the ARM core, however, if they are DMA
enabled, they would also be serviced by the DMA controller to increase system perfor-
mance while the ARM core is running from cache.
1.2 Power Supply
The SoC's core logic requires a 1.8 V supply. Digital Input/Output pins are 5 V tolerant
and require a 3.3 V supply. They are designed to operate from a single 3.3 V supply. An
on-chip 1.8 V-to-3.3 V linear regulator can be used to generate the 1.8 V needed by
the core logic.
1.2.1 Linear Regulator
When the linear regulator is enabled, the 1.8 V power pins (VDDC) are outputs of the
regulator. This allows regulator operation verification. In addition, an external low-ESR
capacitor must be tied to the regulator output for stability. If the regulator is disabled, the
1.8 V power pins are used as inputs from an external 1.8 V supply.
The linear regulator is enabled by tying the LINREGEN pin to 3.3 V; it is disabled by
holding the LINREGEN pin LOW. Proper power-up sequencing must be considered when
employing the linear regulator. In order to ensure this takes place, nRESETIN must be held
LOW until the linear regulator has ramped up to nominal operating voltage.
The linear regulator must only be used to power the SoC and internal devices; it is not
intended to supply power to off-chip peripherals. Powering external devices can result in
unpredictable behavior or device failure.
1.2.2 Phase Locked Loop Power
Two PLLs provide accurate, on-board clocks (see Section 1.3). The PLLs require a 1.8 V
supply. If the linear regulator is disabled, the supply must come from an external source.
If the linear regulator is enabled, the PLL power supply comes from the internal VDDC
power pins.
Version 1.0
Overview
1-3
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