Wdt Operation Details - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

19.1.1 WDT Operation Details

The WDT is enabled and disabled by programming the CTL:EN bit to 1. To reset the WDT,
program the Reset register (RST) with the value 0x1984. To prevent the WDT from being
inadvertently disabled, the Enable function can be locked by setting the CTL Freeze field
(CTL:FRZ).
To configure the initial value, program the CTL Timeout Period field (CTL:TOP). The value
in TOP specifies one of 16 time-out periods, ranging from 2
When the WDT is enabled or reset, the value in CTL:TOP is loaded into the Count registers
(COUNT[3:0]) and the WDT starts decrementing.
COUNT[3:0] are a set of registers operating as a cascaded counter, reporting the current
WDT decrementing value:
• COUNT3 contains bits 31 through 24 of the current value.
• COUNT2 contains bits 23 through 16 of the current value.
• COUNT1 contains bits 15 through 8 of the current value.
• COUNT0 contains bits 7 through 0 of the current value.
When all of COUNT[3:0] are 0, the WDT has timed out. Software can set WDT operation
to cause a system reset, or an interrupt followed by a system reset:
• To cause a system reset after one WDT timeout, program the CTL Interrupt First
bit (CTL:IF) to 0.
• To generate an interrupt after one WDT timeout, and a reset only if the interrupt is not
serviced, program CTL:IF to 1. The first timeout sends an interrupt to the Vectored
Interrupt Controller (VIC). This interrupt is also reported in the Status register INT
field (STATUS:INT). Unless software services this interrupt and resets the WDT, a
second (and subsequent) timeout causes a reset. Interrupts are generated until a
counter reset is performed, even if the counter has been disabled after the first interrupt
was generated.
– The VIC allows programming the type of interrupt (IRQ or FIQ) generated by the
WDT. Bit 0 in the VIC's INTSELECT register can be programmed to 1 to generate an
FIQ, or 0 to generate an IRQ. After reset, this bit is programmed to 0, for an IRQ.
CAUTION
Once set, FRZ can only be cleared by a system reset. Ensure
that the WDT will always be serviced by software before
freezing the Enable bit.
Version 1.0
Watchdog Timer
16 31
through 2 HCLK cycles.
19-3