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Real Time Clock
The value of the counter can be read by software from the Data Register (DR). This value
changes every second. The RTC can be programmed to generate the RTC Interrupt when
a value, programmed into the Match Register (MR), is reached. Program the Load Register
(LR) to the timing start value. The elapsed real time is the difference between the value pro-
grammed in the LR and the value in the MR, in seconds (taking into account count wrapping).
To use the RTC Interrupt, it must be unmasked (programming IMSC:IMSC to 1). In
addition, the interrupt must be enabled in the Vectored Interrupt Controller (VIC). The
VIC register/bit INTENABLE:(bit 15) = 1. Other VIC registers that must be programmed
include bit 15 of the INTSELECT register, and to assign a interrupt vector address using
VECTADDRx and VECTCTRLx.
The interrupt is generated from HCLK so there is no delay between reaching the Match
value and generating the RTC Interrupt.
Before using the RTC following reset, clear any pending interrupts (write 0x0001 to the ICR
register) before enabling interrupts and/or RTC counting.
The RTC is reset by nRESETIN or by a software reset.
12.1.1 Configuring the RTC for Use
To configure the RTC:
1.
Set the initial counter value by writing the value to the LR. This value becomes valid
on the next CLK1HZ rising edge.
2.
Set the interrupt trigger value by writing the value to the MR.
3.
Clear pending interrupts to eliminate spurious interrupts that may have been gener-
ated at reset by writing 0x0001 to the ICR register.
4.
Enable the RTC by programming the CR to 0x0001. Program the IMSC to 0x0001 to
unmask the RTC Interrupt as the RTC Interrupt is masked following reset.
5.
The RTC Interrupt can be masked by programming the IMSC to 0x0000 (the reset value).
The difference in values between LR and MR is the number of seconds that will elapse
between starting the counter and interrupt generation.
The interrupt can be read in the Raw Interrupt Status Register (RIS). If the interrupt is not
masked in the IMSC, it is also asserted to the VIC. Software can clear the interrupt by writ-
ing to the Interrupt Clear Register (ICR).
Note that the counter will continue to match the MR contents until updated one full second
later on the next CLK1HZ rising edge. If software attempts to clear the interrupt during this
period, another interrupt will be immediately generated. This should be taken into account
when programming the RTC.
12-2
Version 1.0
LH79524/LH79525 User's Guide
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