Table 7-50. Dynrascasx Register; Table 7-51. Dynrascasx Fields; Dynamic Memory Ras And Cas Delay Register For Ndcs0 And Ndcs1 (Dynrascasx) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
7.5.2.20 Dynamic Memory RAS and CAS Delay Register for
nDCS0 and nDCS1 (DYNRASCASx)
The Dynamic Memory RAS and CAS Delay Register selects the RAS and CAS latencies
for the relevant dynamic memory. Note that the same value must be programmed into the
device's Mode register.
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:10
9:8
7:2
1:0
NOTE: *The RAS to CAS latency (RAS) and CAS latency (CAS) are both defined in HCLK clock cycles.

Table 7-50. DYNRASCASx Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 7-51. DYNRASCASx Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
CAS Latency
00 = reserved
CAS*
01 = one clock cycle
10 = two clock cycles
11 = three clock cycles
/// Reserved Reading returns 0. Write the reset value.
RAS Latency
00 = reserved
RAS*
01 = one clock cycle
10 = two clock cycles
11 = three clock cycles
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
CAS
0 1 1 0
RO RW RW RW
0xFFFF1000 + 0x104 for DYNRASCAS0
0xFFFF1000 + 0x124 for DYNRASCAS1
FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
///
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
RAS
1 1
RW RW
7-51