Table 7-11. Control Register; Table 7-12. Control Fields; Register Definitions - Sharp LH79524 User Manual

External Memory Controller

7.5.2 Register Definitions

7.5.2.1 Control Register (CONTROL)
The CONTROL Register controls the memory controller operation. The control bits can be
altered during normal operation.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:3
2
1
0
7-30

Table 7-11. CONTROL Register

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
0 0 0 0
RO RO RO RO RO

Table 7-12. CONTROL Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Mode select Entering low-power mode reduces memory controller power
consumption. Dynamic memory is refreshed as necessary. The memory con-
troller returns to normal functional mode by clearing the low-power mode bit.
External memory cannot be accessed in low-power state. If a memory access
MODE
is performed, an error response is generated.
1 = Low-power Mode
0 = Normal Mode
/// Reserved Reading returns 0. Write the reset value.
Enable the EMC Disabling the External Memory Controller reduces power
consumption. When the memory controller is disabled the memory is not re-
freshed. The memory controller is enabled by setting the enable bit. The exter-
nal memory cannot be accessed in disabled state. If a memory access is
ENABLE
performed, an error response is generated.
1 = Enabled
0 = Disabled
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x000
FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RW
17 16
0 0
RO RO
1 0
///
0 1
RW RW