Sharp LH79524 User Manual page 121

LH79524/LH79525 User's Guide Color Liquid Crystal Display Controller
Table 4-19. TIMING2 Fields (Cont'd)
BIT NAME DESCRIPTION
Invert the Vertical Synchronization Signal IVS selects the polarity of the LCDFP signal.
11 IVS
1 = LCDFP is active LOW
0 = LCDFP is active HIGH
AC Bias Signal Frequency ACB sets the frequency of the LCDEN signal.
STN modes: ACB applies to the CLCDC when it is operating in the STN mode. STN
displays require periodic reversal of the pixel voltages in order to prevent damage to
the STN panel due to DC charge accumulation. Program this field to select the required num-
10:6 ACB
ber of line clocks (the LCDLP signal) between each toggle of the AC bias signal (LCDEN).
ACB = (line clocks) – 1
TFT modes: This field has no effect if the CLCDC is operating in TFT mode because the
LCDEN pin is instead utilized for a Data Enable signal.
/// Write the reset value
5 Reserved Reading returns 0. .
Panel Clock Divisor Program this field and the PCD_HI field to select the LCD panel
clock frequency (LCDDCLK frequency) from the input CLCDC CLOCK frequency.
LCDDCLK = (CLCDC CLOCK)/(PCD+2)
Mono STN modes: LCDDCLK for mono STN panels with a four- (or eight-) bit interface
should be programmed to be 1/4 (or 1/8) the desired individual pixel clock rate.
Color STN modes: Color STN displays receive multiple pixels during each clock cycle. The
4:0 PCD_LO
pixel data for Color STN displays is stored and transferred in packed format, with each pixel
represented by three bits (R,G and B). Therefore, one byte contains the pixel data for 2 2/3
pixels (RGB, RGB, RG) and three bytes contain the pixel data for eight complete pixels. For
Color STN panels, each LCDDCLK cycle transfers one byte, containing 2 2/3 pixels, to the
panel. LCDDCLK should be programmed to be as close as possible to 3/8 the desired indi-
vidual pixel clock rate.
TFT mode: For TFT displays, the pixel clock divider can be bypassed by programming
TIMING2:BCD = 1.
Version 1.0 4-25