Table 17-48. Intr Register; Table 17-49. Intr Fields; Pending Dma Interrupts Register (Intr) - Sharp LH79524 User Manual

Universal Serial Bus Device

17.2.3.13 Pending DMA Interrupts Register (INTR)

This register indicates the status of pending DMA interrupts
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
17-32

Table 17-48. INTR Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
BITS NAME
31:6
/// Reserved Reading returns 0. Write the reset value.
Channel 6 Interrupt Status
5 INTR6
1 = Interrupt pending from DMA Channel 6
0 = No pending interrupt
Channel 5 Interrupt Status
4 INTR5
1 = Interrupt pending from DMA Channel 5
0 = No pending interrupt
Channel 4 Interrupt Status
3 INTR4
1 = Interrupt pending from DMA Channel 4
0 = No pending interrupt
Channel 3 Interrupt Status
2 INTR3
1 = Interrupt pending from DMA Channel 3
0 = No pending interrupt
Channel 2 Interrupt Status
1 INTR2
1 = Interrupt pending from DMA Channel 2
0 = No pending interrupt
Channel 1 Interrupt Status
0 INTR1
1 = Interrupt pending from DMA Channel 1
0 = No pending interrupt
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF5000 + 0x200

Table 17-49. INTR Fields

FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
.
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO