Table 4-26. Ctrl Register; Clcdc Control Register (Ctrl) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

4.5.3.7 CLCDC Control Register (CTRL)

CTRL controls the CLCDC operating mode. All registers should be set up prior to program-
ming LCDEN to 1.
Note that the operating mode (color/mono, bits-per-pixel, etc.) can only be changed
between frames to avoid corruption of the current frame data. To ensure this is done prop-
erly, use the Vertical Compare Interrupt to detect that the current frame is complete. To do
this, follow these steps when changing operating mode:
1. Program the CTRL: VCI bit to 0b00 to generate the Vertical Compare Interrupt on entry
to the Sync State. Enable this interrupt by programming the INTREN:VCIEN bit to 1.
2. Program the CTRL:LCDEN bit to 0. The controller will complete the current frame
before sampling this bit.
3. Wait for the Vertical Compare Interrupt. Upon assertion of the interrupt, program the
new mode (e.g. from color to monochrome using the CTRL:BW bit).
Then program the CTRL:LCDEN bit to 1 and clear the Vertical Compare Interrupt by writ-
ing a 1 to the STATUS:VCI bit. The CLCDC will resume operating, using the newly pro-
grammed parameters.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 4-26. CTRL Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RW RW RW RW RW
Color Liquid Crystal Display Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RW RW
0xFFFF4000 + 0x1C
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
BPP
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RW
1 0
0 0
RW RW
4-29