Table 18-5. Fiqstatus Register; Table 18-6. Fiqstatus Fields; Table 18-7. Rawintr Register; Table 18-8. Rawintr Fields - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
18.2.2.2 FIQ Status Register (FIQSTATUS)
This Read Only register provides the status of the interrupts after FIQ masking. Bits [31:0]
correspond to the interrupt number in Table 18-1.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:0 FIQStatus
18.2.2.3 Raw Interrupt Status Register (RAWINTR)
This Read Only register provides the status of the source interrupts (and software
interrupts) to the VIC. Bits [31:0] correspond to the interrupt number in Table 18-1.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:0

Table 18-5. FIQSTATUS Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 18-6. FIQSTATUS Fields

NAME
Interrupt Status After Masking Shows the status of the interrupts after
masking by the IntEnable and IntSelect Registers.
For each bit:
1 = Interrupt is active and generates an FIQ exception to the ARM7 core
0 = Interrupt is not active

Table 18-7. RAWINTR Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 18-8. RAWINTR Fields

NAME
Raw Interrupt Status
before masking by the Interrupt Enable Registers.
RawInterrupt
For each bit:
1 = Appropriate interrupt request is active before masking
0 = Appropriate interrupt request is not active before masking
26 25 24 23
FIQStatus
0 0 0 0
RO RO RO RO
10 9 8 7
FIQStatus
0 0 0 0
RO RO RO RO
0x004
0xFFFFF000 +
DESCRIPTION
26 25 24 23
RawInterrupt
0 0 0 0
RO RO RO RO
10 9 8 7
RawInterrupt
0 0 0 0
RO RO RO RO
0x008
0xFFFFF000 +
DESCRIPTION
Shows the status of the interrupts
Version 1.0
Vectored Interrupt Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO
18-7