Table 13-16. Sysclkpre Register; Table 13-17. Sysclkpre Fields; Table 13-18. Sysclkpre Register Values; System Clock Prescaler Register (Sysclkpre) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.7 System Clock Prescaler Register (SYSCLKPRE)

HCLK is the System Clock. This register allows a divisor to be programmed that is used to
divide the system PLL frequency to derive HCLK. The prescaled HCLK frequency is
defined by:
ƒ(HCLK)
Following reset, the prescaler is programmed to divide by 30. Table 13-18 shows example
values for HDIV.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:4
3:0
⎛ ƒ(SystemPLL) ⎞
ƒ ------------------------------------- -
=
⎝ ⎠
×
2 HDIV

Table 13-16. SYSCLKPRE Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-17. SYSCLKPRE Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
HCLK Divisor Program with the divisor for the HCLK prescaler. All
HDIV
HDIV combinations are valid except 0b0000.

Table 13-18. SYSCLKPRE Register Values

HDIV
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
:
0b1111 (default)
Reset, Clock, and Power Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE2000 + 0x18
DESCRIPTION
DIVISOR
—
2 ƒ(System PLL)/2
4 ƒ(System PLL)/4
6 ƒ(System PLL)/6
8 ƒ(System PLL)/8
10 ƒ(System PLL)/10
:
30 ƒ(System PLL)/30
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 1
RO RO RO RW RW
ƒ(HCLK)
Invalid
:
17 16
0 0
RO RO
1 0
HDIV
1 1
RW RW
13-17