Clock Divider Control Register A (Crda) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
5.1.5.

Clock divider control register A (CRDA)

This register controls clock divider.
Address
Bit 31 30 29
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name (Reserved) ARMBDM[2:0]
R/W R0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit field
No. Name
31-16 –
15 (Reserved)
14-12 ARMBDM[2:0] ARMBCLK frequency dividing mode
11-9 ARMADM[2:0] ARMACLK dividing mode
8-6 Reserved
28 27 26 25
– – – –
X X X X
12 11 10 9
ARMADM[2:0]
1 0 0 0
Unused bits.
Write access is ignored, and read value of these bits is undefined.
Reserved bit.
Write access is ignored, and read value of these bits is always "0".
These bits set frequency dividing ratio of ARMBCLK.
× (1/1)
000 f
= f
ARMBCLK CCLK
× (1/2) (initial value)
001 f
= f
ARMBCLK CCLK
× (1/4)
010 f
= f
ARMBCLK CCLK
× (1/8)
011 f
= f
ARMBCLK CCLK
× (1/16)
100 f = f
ARMBCLK CCLK
Others Reserved (setting prohibited)
f : Clock frequency of ARMBCLK
ARMBCLK
f : Clock frequency of CCLK
CCLK
These bits set frequency dividing ratio of ARMACLK.
× (1/1) (initial value)
000 f
= f
ARMACLK CCLK
× (1/2)
001 f = f
ARMACLK CCLK
× (1/4)
010 f = f
ARMACLK CCLK
× (1/8)
011 f
= f
ARMACLK CCLK
× (1/16)
100 f
= f
ARMACLK CCLK
Others Reserved (setting prohibited)
f : Clock frequency of ARMACLK
ARMACLK
f : Clock frequency of CCLK
CCLK
FFFE_7000 + 10
H H
24 23 22 21
– – – –
X X X X
8 7 6 5
reserved[2:0]
0 1 1 0
Description
20 19 18 17
– – – –
X X X X
4 3 2 1
PADM[2:0] HADM[2:0]
1 1 0 1
16
–
X
0
0
5-25