I2Sxcntreg Register - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

27.6.5 I2SxCNTREG register

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MSKB MSMD SBFN RHLL ECKM BEXT FRUN MLSB TXDIS RXDIS SMPL CPOL FSPH FSLN FSPL

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ch0：FFEE_0008 (h)

This sets output clock frequency dividing ratio at master operation.

AHB clock is divided at ECKM = 0, and external clock is divided at ECKM = 1. Only

even number of the ratio is supported and output clock's DUTY becomes 50%. CKRT

[5:0] × 2 becomes number of AHB clock or external clock cycle included in 1 cycle

Setting examples are shown below.

External clock mode and external clock are 24.576MHz:

Internal clock mode and AHB clock are 80MHz:

Frame rate is able to be adjusted by inserting OVHD bit following to valid data of the

frame. OVHD section of the transmission frame becomes in high impedance. Up to 0

– 1023 OVHD bit is able to be inserted, and is inserted at the end of the frame.

The value set to OVHD becomes the number of insertion bit.

The following expressions are formed for OVHD and frame synchronous signal cycle

1 sub frame construction:

OVHD = Frame synchronous signal cycle/I2S_SCKx cycle – (S0CHL + 1) × (S0CHN + 1)

2 sub frame construction:

OVHD = Frame synchronous signal cycle/I2S_SCKx cycle – (S0CHL + 1) × (S0CHN + 1)

– (S1CHL + 1) × (S1CHN + 1)

(external clock is output as it is)