Interrupt Enable Register (Urtxier) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.6.4 Interrupt enable register (URTxIER)

ch0：FFFE_1000 + 04h ch1：FFFE_2000 + 04h ch2：FFF5_0000 + 04h
Address
ch3：FFF5_1000 + 04h ch4：FFF4_3000 + 04h ch5：FFF4_4000 + 04h
Bit 31 30 29
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
valu X X X
e
Bit No. Bit name
Unuse
31:4
d
3 EDSSI
2 ELSI
1 ETBEI
0 ERBFI
Interrupt can be disabled by setting "0" to all bits of bit3:0.
All interrupt factors of the bit set "1" in bit3:0 become valid.
(Accessing is enabled only at DLAB = 0)
28 27 26 25
X X X X
12 11 10 9
(Reserved)
X X X X
Reserved bit (input "0" at writing)
Enable Modem Status Interrupt
When EDSSI is set to "1" and bit3:0 of the Modem status register is set, interrupt
occurs.
Enable Receiver Status Interrupt
When ELSI is set to "1" and bit4:1 of the Line status register is set, interrupt occurs.
Enable Transmitter FIFO Register Empty Interrupt
After ELSI is set to "1", interrupt occurs when Transfer FIFO register becomes
empty.
Enable Receiver FIFO Register
When ERBFI is set to "1" and reception FIFO reaches to the trigger level, interrupt
occurs. (Interrupt also occurs when character time-out occurs.)
24 23 22 21
(Reserved)
X X X X
8 7 6 5
(Reserved)
X 0 0 0
Function
20 19 18 17
X X X X
4 3 2 1
EDSSI ELSI ETBEI ERBFI
0 0 0 0
28-7
16
X
0
0