I2Sxsrst Register - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
27.6.10

I2SxSRST register

This register is to control I2S software reset.
Address
Bit 31 30 29
Name
R/W R R R
Initial 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial 0 0 0
Bit field
No. Name
31-1 (Reserved)
0 SRST
ch0：FFEE_001C (h)
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
R R R R
0 0 0 0
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
Software reset is performed by writing "1".
STATUS register and each internal state machine become initial state by software
reset, and transmission/reception FIFO becomes empty.
There is no influence in registers other than STATUS, INTCNT, and DMAACT registers.
When read value is "0" after writing "1", it indicates software reset is completed. "1"
indicates software reset is in process.
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
(Reserved)
R R R R
0 0 0 0
Description
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
SRS
R R R R R/W
0 0 0 0
27-15
16
R
0
0
T
0