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MB86R02 'Jade-D' Hardware Manual V1.64
11.6.2 SRAM/Flash timing register 0/2/4 (MCFTIM0/2/4)
Register address
Bit No.
31
Bit field name
R/W
Initial value
Bit No.
15
Bit field name
R/W
Initial value
Bit31-28: WIDLC (Write Idle Cycle: Write idle cycle)
These bits set the number of idle cycle after the write access. When RDY bit is set to
"1", specify 2 or more value.
0
|
|
15
Bit27-24: WWEC (Write Enable Cycle)
These bits set the number of write enable assertion cycle. This setting also affects to
MEM_XWR[3:0]. When RDY bit is set to "1", the value should be 3 or more (4 cycles
or more.)
0
|
|
5
|
|
14
15
Bit23-20: WADC (Write Address Setup cycle)
These bits set number of write access setup cycle. Address is output to the cycle
however write enable is not asserted. When RDY bit is set to "1", the value should be
1 or more (2 cycles or more.)
0
|
|
5
|
|
14
15
BaseAddress + 0x0020(MEM_XCS[0]),
BaseAddress + 0x0028(MEM_XCS[2]),
BaseAddress + 0x0030(MEM_XCS[4])
30
29
28
27
26
WIDLC
WWEC
0
14
13
12
11
10
RIDLC
FRADC
15
1 cycle (initial value)
16 cycles
1 cycle
6 cycles (initial value)
15 cycles
Reserved
1 cycle
6 cycles (initial value)
15 cycles
Reserved
25
24
23
22
21
WADC
R/W
5
5
9
8
7
6
5
RADC
R/W
0
0
20
19
18
17
16
WACC
15
4
3
2
1
0
RACC
15
11-5
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