Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
4 CPU (ARM926EJ-S core)
This chapter describes the embedded CPU core (ARM926EJ-S core) of the MB86R02 'Jade-D'
device.
4.1 Outline of ARM926EJ-S core
The major functional blocks of the ARM926EJ-S core are the TMC (Tightly Coupled Memory) and the
ETM9CS Single modules.
4.2 Features of ARM926EJ-S core
The ARM926EJ-S core offers the following features:
•
Five-stage pipeline (fetch, decode, execution, memory and writing)
•
Harvard architecture
•
16KB instruction cache / 16KB data cache
•
16KB instruction TCM (ITCM) / 16KB data TCM (DTCM)
•
JAVA acceleration (Jazelle technology)
•
Coprocessor interface
•
MMU (Memory Management Unit)
•
Embedded ETM9CS Single for real-time tracing
•
Supports both big and little endian
4.3 Block diagram of ARM926EJ-S core
The block diagram of the ARM926EJ-S core is shown in Figure 4-1.
JTAG
Signals
ARM926EJ-S Core Block
ARM926EJ-S
16kB
Instruction
16kB
TCM
Instruction
Cache
JTAG
Sync.
Circuit
Instruction AHB
Figure 4-1 Block diagram of ARM926EJ-S core
Trace Signals
(4bit TRACEPKT)
ETM9CS
Single
configuration
16kB
Data
16kB
TCM
Data
Cache
AHB I/F
Data AHB
4-1
Advertisement
Table of Contents
