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MB86R02 'Jade-D' Hardware Manual V1.64
Bit
init
Name
:
ial
cfg_pxdata_width[1]
7
1
cfg_pxdata_width[0]
6
0
cfg_px_out_ctrl_piggyback[1]
5
1
cfg_px_out_ctrl_piggyback[0]
4
1
Reserved
3
1
Reserved
2
1
Reserved
1
0
Reserved
0
0
Table 17-3 RX config_byte_2
config_byte_2
Description
APIX PHY
bit width of pixel data
00: 10 bits
01: 12 bits
10: 18 bits
11: 24 bits
Note: width of pixel data setting has
to match related transmitter device
configuration
APIX PHY
transmission of pixel control signals
(px_ctrl[2:0], used for HSYNC, VSYNC,
DE)
00: never
01: unused
10: with even pixels only
11: with every pixel
Note: pixel control signals setting
has to match related transmitter
device configuration
Note: to achieve maximum pixel link
net bandwidth setting "10" is
necessary, see APIX standard
do not change
do not change
do not change
do not change
17-17
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