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MB86R02 'Jade-D' Hardware Manual V1.64
TIS (Tile Size)
Register
DrawBaseAddress + 468
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register specifies the tile size (m, n).
Bit 6 to 0
TISM (Title Size M)
Sets horizontal tile size. Any power of 2 between 4 and 64 can be used. Values that are
not a power of 2 cannot be used.
0.000100
0001000
0010000
0100000
1000000
Other than
the above
Bit 22 to 16
TISN (Title Size N)
Sets vertical tile size. Any power of 2 between 4 and 64 can be used. Values that are not
a power of 2 cannot be used.
0000100
0001000
0010000
0100000
1000000
Other than
the above
TOA (Texture Buffer Offset address)
Register
DrawBaseAddress + 46C
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
This register sets the texture buffer offset address. Using this offset value, texture patterns can be
referred to the texture buffer memory.
Specify the word-aligned byte address (16 bits). (Bit 0 is always "0".)
H
TISN
RW
1000000
M=4
M=8
M=16
M=32
M=64
Setting disabled
N=4
N=8
N=16
N=32
N=64
Setting disabled
H
TISM
RW
1000000
XBO
RW
Don't care
18-223
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