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MB86R02 'Jade-D' Hardware Manual V1.64
25.3
Block diagram
Figure 14-1 shows a block diagram of the PWM unit.
PWM module
IRC
Int0..7
25.4
Related pins
The availability of PWM pins depends on the follow CCNT (JCNT) registers:
• Set to CMPX_MODE_6 = "1
• Set to CMPX_MODE_7 = "0
25.5
Clock Supply
The APB clock is supplied to the PWM unit. Please refer to the chapter 'Clock Reset Generator
(CRG)' for details on setting the frequency and controlling the clock.
25.6
Interrupts
When an interrupt vector occurs, the PWM notifies the IRC. Please refer to the 'Interrupt
Controller (IRC)' chapter for more details.
25-2
PULSE
generator
generator
Figure 25-1 PWM block diagram
" of multiplex mode setting register to make PWM[7:4] available
B
" of multiplex mode setting register to make PWM[3:0] available
B
CLK
PWM_O0
PWM_O1
PWM_O2
8
.
.
PWM_O7
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