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MB86R02 'Jade-D' Hardware Manual V1.64
V1.40
19.10.2009
V1.30
24.07.2009
Words, to the implemented size of 66/132 Words.
CCNT: Modified CCID register fields.
Electrical Characteristics: changes:
(1) Table 34-1 Maximum Ratings
(2) Table 34-3 3.3V Standard CMOS I/O Recommended
Operating Conditions, added driving capabilities.
(3) New section: APIX Characteristics
(4) Added RSDS characteristics
GDC: 18.6.3.3 Direct Color (24 bits/pixel) – corrected RGBA
table (A field is only 1 bit)
GDC: Extended all LxEC descriptions for RGBA (e.g. L1EC,
L2EC etc.)
RLD: byte alignment information added to StrideCfg1 register.
Limitations information added to AHBMTransferWidth Setup
section.
von Treuberg
Overview: Unused pins - changed handling of OSC_FILTER,
changed handling of XTRST pin.
GPIO: re-inserted block diagram (mistakenly removed)
IRC: removed IRQs as only required for debugging
DMAC: Corrected line to MPX_MODE_1[1:0] = "HL" in section
'Related Pins'. Corrected DMA configuration A register
(DMACAx), BC[3:0] and TC[15:0] function descriptions.
RLD: added more detail to DestAddress register description
Electrical characteristics, almost all tables modified
CRG: corrected initial value of CRAM register.
TCON: exchanged Figure 22-4 Block diagram of TSIG.
SSCG: updated register description
UART: changed table 28-2:
(external input condition: CLK = 25.0MHz, CRIPM[3:0] = 0001)
Addendum (differences ES1/ES2): added note about APIX TX
initialization
von Treuberg
CCNT: Corrected typo in description of register CAXI_PS
ADDENDUM: Added note about JTAGSEL polarity
DMAC: changed hex value in second diagram of section
'15.8.1 DMA start in Single channel'
GPIO: corrected base address in table 24-1
DDR2: several small corrections concerning DRIMRx and
OCD adjustment
CCNT: Added note that only 32 bit access to DDR is poss.
when in big endian mode. Extended description of multiplex
mode/function selection register CMUX_MD. Corrected ChipID
register displayed values.
Overview + Addendum: modified MUX tables for better
understanding. Added cell types to pin overview.
Memory map: changed RHlite to APIX, added SSCG area.
Modified Register Access description.
I2C: added 'Example of a slave address transmission'
GPIO: new block diagram and note about configuration of
differential pair configuration in MUX mode 4, function 4
SIG: added limitation for cyclic monitoring mode.
SSCG: added base address to register description.
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