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MB86R02 'Jade-D' Hardware Manual V1.64
Standard mode:
High-speed mode:
Set fscl so that it does not exceed the following values during master operation.
• Standard mode: 100kHz
• High-speed mode: 400kHz
Use the system clock
If it is less than the range, transfer at the max. transfer rate is not guaranteed.
If it exceeds the range, operation is not guaranteed.
• Master operation: 14MHz ~ 41.5MHz
• Slave operation: 14MHz ~ 41.5MHz
• Register access operation: 14MHz ~ 41.5MHz
Note:
+2 cycle is the min. overhead for the detection of the output level change of the SCL
line. If the rising edge delay of the SCL pin is large or the clock is expanded for the
slave device, the value is larger than the one stated above.
If the extension CS register is used, m value becomes CS10 ~ 0 + 1.
φ
=
fscl
2 (
×
)
+
2
m
φ
=
fscl
int(
1
5 .
×
)
+
2
m
int(
: )
Round
φ
of this module within the range shown below.
_
φ
:
APB
clock
( :
10
0)
m
Value
of
CS
φ
:
APBclock
( :
10
0)
1
m
Value
of
CS
off
after
decimal
poin
1
t
29-19
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