I2Sxmcr1Reg Register - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

27.6.7 I2SxMCR1REG register

This register controls enable and disable functions to each channel of sub frame 0.

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

31-0 S0CH31-S0CH00 Name (S0CHxx) of each bit indicates channel number xx of sub frame 0 (e.g. S0CH00

Channel length of the channel constructing sub frame 0 (bit length of channel) is set.

4 - 32 bit of channel length are available but 1 - 6 bit are prohibited. S0CHN needs to

be set to "channel length – 1".

Example 1 S0CHL = "00110": Channel length becomes 7 bit

Example 2 S0CHL = "11111": Channel length becomes 32 bit

The channel length can be set to 32 or less regardless of RHLL value of CNTREG

Word length of the channel constructing sub frame 0 (number of bit in channel) is set.

4 - 32 bit of word length are available but 1-6 bit are prohibited. S0WDL needs to be

set to "word length – 1".

Example 1 S0WDL = "00110": Word length becomes 7 bit

Example 2 S0WDL = "11111": Word length becomes 32 bit

RHLL of CNTREG register is "1": Set word length to 16 or less and channel length to

shorter than the one set to S0CHL

RHLL of CNTREG register is "0": Set word length to 32 or less and channel length to

shorter than the one set to S0CHL

ch0：FFEE_0010 (h)

bit controls 0th channel of sub frame 0.)

Thus, S0CH31 bit controls 31st channel of sub frame 0.

0 The corresponding channel is disabled

Transmission/Reception are not performed to the disabled channel

1 The corresponding channel is enabled

Transmission/Reception are performed to the enabled channel