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MB86R02 'Jade-D' Hardware Manual V1.64
18.7.9 Display control register
DCM0/1 (Display Control Mode 0/1)
Register
DisplayBaseAddress + 0x00 (DCM0)
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
RW RW
Initial value
0
0
Register
DisplayBaseAddress + 0x100 (DCM1)
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
RW RW
Initial value
0
0
This register controls the display count mode. It is not initialized by a software reset. This register is
mapped to two addresses but it is one substance. The differences between the two registers are
the format of the frequency division rate setting (SC) and layer enable. The two formats exist to
maintain backword compatibility with previous products.
Bit 1 to 0
SYNC (Synchronize)
Set synchronization mode
X0
Non-interlace mode
10
Interlace mode
11
Interlace video mode
Bit 2
ESY (External Synchronize)
Sets external synchronization mode
0:
External synchronization disabled
1:
External synchronization enabled
Bit 3
SF (Synchronize signal format)
Sets format of synchronization (VSYNC, HSYNC) signals
0:
Negative logic
1:
Positive logic
Bit 6
ODE
Odd/Even detect (TBD)
Bit 7
EEQ (Enable Equalizing pulse)
Sets CCYNC signal mode
18-66
Reserve
RX
RW RW RW RW RW
0
0
Reserve
RX
RW RW RW RW RW RW RW RW
X
0
0
0
0
Resv
SC
R0
RW
0
0
0
0
1110
SC
RW
0
0
0
0
11101
SYNC
RW RW RW R0 RW RW
RW
0
0
0
0
0
0
00
SYNC
RW RW RW R0 RW RW
RW
0
0
0
0
0
0
00
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