Arm Core Clock Gate Control Register (Cram); Dperi Clock Gate Control Register (Crdp0, Crdp1) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
5.1.11.

ARM core clock gate control register (CRAM)

This register controls clock gate of ARM core.
Address
Bit 31 30 29
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R1 R1 R1
Initial value X X X
Bit field
No. Name
31-16 –
15-5 (Reserved)
4 ARMBGATE
3-1 (Reserved)
0 ARMAGATE
5.1.12.

DPERI clock gate control register (CRDP0, CRDP1)

(CRDP0 is related to DPERI0
Address
Bit 31 30 29
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value – – –
Bit 15 14 13
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value - - -
Bit field
No. Name
5-32
28 27 26 25
– – – –
X X X X
12 11 10 9
(Reserved)
R1 R1 R1 R1
X X X X
Unused bits.
The write access is ignored, and read value of these bits is undefined.
Reserved bits.
Write access is ignored, and read value of these bits is always "0".
ARMBCLK clock gate control
These bits control ARMBCLK clock gate.
0 ARMBCLK stops
1 ARMBCLK does not stop (initial value)
This clock is used to ATCLK of ETM9CS Single.
Reserved bits.
Write access is ignored, and read value of these bits is always "1".
ARMACLK clock gate control
These bits control ARMACLK clock gate.
0 ARMACLK stops
1 ARMACLK does not stop (initial value)
After stopping this clock, proceed system reset to resume operation.
1
, CRDP1 is related to DPERI1
BaseAdr
28 27 26 25
– – – –
– – – –
12 11 10 9
– – – –
- - - -
FFFE_7000 + 28
H H
24 23 22 21
– – – –
X X X X
8 7 6 5
R1 R1 R1 R1
X X X X
Description
2
)
+ 2C BaseAdr + 30
H H, H H
24 23 22 21
– – – –
– – – –
8 7 6 5
– – - -
- - - -
Description
20 19 18 17
– – – –
X X X X
4 3 2 1
ARMBG
(Reserved)
ATE
R/W R1 R1 R1
1 1 1 1
20 19 18 17
– – – –
– – – –
4 3 2 1
DCGATE
1 1 1 1
16
–
X
0
ARMAG
ATE
R/W
1
16
–
–
0
1